This paper describes the implementation of an APC-AB codec using a single-chip DSP. To handle the simultaneous 8- or 16-kb/s encoding and decoding with a single-chip DSP, we precisely evaluated arithmetic bit accuracy, simplifying the DSP algorithm and sharing subroutines. We designed a dedicated DSP with a 16E8 floating-point data format and a novel DMA control circuit. The 100 X 68 mm codec module contains 2 K words of RAM, a 12-ms echo canceler, and two interface LSI chips. An SNR of 39 dB for 16-kb/s coding and 36 dB for 8-kb/s coding were obtained using method 2 of CCITT recommendation G.712. The module consumes less than 1.0 watt.
Bibliographic reference. Satoh, Kazumi / Kurihara, Hideaki / Unagami, Shigeyuki / Kajihara, Masanori / Tomita, Yoshihiro (1989): "8- and 16-kb/s APC-AB voice codec using a single chip DSP", In EUROSPEECH-1989, 1318-1321.