A multiprocessor architecture for high complexity speech processing is described that uses groups of 4 DSP chips each in a hierarchical, reconfigurable structure, yielding some 100 MFlops per board. This architecture combines low amount of hardware with high efficiency for many speech applications. The software environment is based on available development tools and can easily be adapted to future DSP components.
Cite as: Schultheiß, M., Lacroix, A. (1991) Fast hardware for efficient parallel processing of speech signals. Proc. 2nd European Conference on Speech Communication and Technology (Eurospeech 1991), 1353-1356, doi: 10.21437/Eurospeech.1991-309
@inproceedings{schulthei91b_eurospeech,
author={M. Schultheiß and A. Lacroix},
title={{Fast hardware for efficient parallel processing of speech signals}},
year=1991,
booktitle={Proc. 2nd European Conference on Speech Communication and Technology (Eurospeech 1991)},
pages={1353--1356},
doi={10.21437/Eurospeech.1991-309}
}