This paper analyses the parametric speech synthesizer by D. H. Klatt [1, 2] from the point of view of designing an Application Specific Instruction Set Processor (ASIP) chip for parametric speech synthesis. By analyzing Klatt's code, the frequency of different computational operations in the code is estimated and constraints on speeds in performing these operations are derived. Next, the definition of a suitable instruction set for the ASIP and the hardware architecture for its implementation are proposed and analyzed. The architecture is verified using VHDL modeling and simulation. The strategy of implementation of the instruction set on the proposed hardware architecture is discussed and estimates of equivalent gate counts and RAM blocks needed for FPGA realization are given.
s D. H. Klatt, "Software for a cascade/parallel formant synthesizer," J. Acoust. Soc. Am 67, 971-995, 1980. D. H. Klatt, "Review of text-to-speech conversion for English", J. Acoust. Soc. Am. 82, 737-793, 1987.
Cite as: Saini, R., Srivastava, S., Mandal, A.S., Kumar, S., Singh, R., Karmarkar, A., Shekhar, C. (2003) Architecture of an application-specific instruction set processor for parametricspeech synthesis. Proc. Workshop on Spoken Language Processing, 171-175
@inproceedings{saini03_wslp,
author={R. Saini and S. Srivastava and A. S. Mandal and Sudhir Kumar and R. Singh and A. Karmarkar and C. Shekhar},
title={{Architecture of an application-specific instruction set processor for parametricspeech synthesis}},
year=2003,
booktitle={Proc. Workshop on Spoken Language Processing},
pages={171--175}
}